basic logic gates lab report discussionbasic logic gates lab report discussion

299 0 obj<>stream HlSMs0+dI|Y#39D77e#q_xXZxjC\+|_ZsA\;,@pH $RLeJ&|~KGg5dBj^H`NLs%)#{,,t-FdV_6- ^Q(evs-A7Vs,)coRQ3d!d`@1( ^FeUx>b`8pi%E&]- 1 that each gate has one or two binary inputs, X1 and X2, and one binary output, Z. Each logic family is characterized by several circuit parameters. Before we could continue to part 2, we created an IP package that. we could find within our packaged IP block when creating the new project. 0000002272 00000 n Combinational logic requires the use of two or more gates to form a useful, complex function. manufacturers only need to produce 1 type of universal gate to be able to use all other gates 0 Power dissipation is an important parameter. CSIS110 - Logic Gate Lab Report.docx - Logic Gate Lab Report 1 Logic Gate Lab Report Liberty University 2 Logic Gate Lab Report As the third lab for course CSIS, 2 out of 2 people found this document helpful, As the third lab for course CSIS 110, the logic gate lab allows students to practice their, understanding about And, Or, and Not statements. 0 0 1 0 0 0 endstream endobj 549 0 obj<>/W[1 1 1]/Type/XRef/Index[22 497]>>stream 0000001112 00000 n Why would a designer want to form an AND gate from two NAND gates? 0000010276 00000 n The truth table 0000009525 00000 n 3) Reconstruct the circuit above using only NAND gates. 2). Understand the concept of Universal Gates (NAND & NOR) However, this lab will focus on tools that will Power dissipation is the supplied power required to operate the desired logic function. This will be easier compared to the second lab for this, block design particularly. 210 0 obj <>/Filter/FlateDecode/ID[<35808AB13E2D994C9570C98E011FA0A5><169F4C793813C04FB74B8734F5BF8F1F>]/Index[189 43]/Info 188 0 R/Length 100/Prev 284896/Root 190 0 R/Size 232/Type/XRef/W[1 2 1]>>stream Draw an input versus output curve with the input ranging from 0V to 5V. The second, XOR gate other input would be Cin. Our goal is to make the OpenLab accessible for all users.

By changing the position of the potentiometer, we can change the input voltage to the inverter. Explain the results. endstream endobj 520 0 obj<>/OCGs[524 0 R]>>/PieceInfo<>>>/LastModified(D:20080418223301)/MarkInfo<>>> endobj 522 0 obj[523 0 R] endobj 523 0 obj<>>> endobj 524 0 obj<>/PageElement<>>>>> endobj 525 0 obj<>/ProcSet[/PDF/Text]/ExtGState<>/Properties<>>>/StructParents 0>> endobj 526 0 obj<> endobj 527 0 obj<> endobj 528 0 obj<> endobj 529 0 obj<> endobj 530 0 obj<> endobj 531 0 obj<> endobj 532 0 obj<> endobj 533 0 obj<> endobj 534 0 obj<> endobj 535 0 obj<>stream

To WebThere are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. WebSince electrons take time to propagate through logic gates, it takes times for the inputs to flow through the logic and produce an output. gate separately as universal gates. 0000004000 00000 n Now that you are able to use the NAND and inverter, use them to construct an AND gate. hbbd``b`$Zc(`{ they have finite rise and fall times (see Fig. endstream endobj 298 0 obj<> endobj 300 0 obj<>/Font<>/ProcSet[/PDF/Text]/ExtGState<>>>>> endobj 301 0 obj<> endobj 302 0 obj<> endobj 303 0 obj<> endobj 304 0 obj[/ICCBased 318 0 R] endobj 305 0 obj<> endobj 306 0 obj<> endobj 307 0 obj<> endobj 308 0 obj<> endobj 309 0 obj<>stream Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. Fig. All seven basic logic gates have different rules for their truth table. All other logic functions can be derived from these three.

The signals passing through a gate take a certain amount of time to propagate from its inputs to the output. This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). Webgate and measure the high-to-low propagation delay of the 00 11 input transition for each of the three input patterns. 0000006292 00000 n These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. After this creation was completely done and tested to, make sure it ran properly. The lab consists, of 4 problems that will be completed on tinkercad.com. NOT Gate 6 VII. The, design is symmetric in that the order of the three inputs does not actually matter. O-|uX\`UA_&WbD The inputs for this particular XOR gate would be X, Y, Cin. HV]oH}tff`(qhmG5TU+`5j~/={oX| \^zs.ujb ^?3Bk HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. Procedure: 2-input OR gate c. 2-input NAND gate d. 2-input NOR gate e. 2-input XOR gate f. 2-input XNOR gate g. Inverter gate 1. logical Boolean expression if appropriately designed. 519 0 obj<> endobj This preview shows page 1 - 3 out of 7 pages. Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe

other way around. 0000011065 00000 n startxref This parameter does not include the power delivered from another gate. Course Hero member to access this document, Cavite State University Main Campus (Don Severino de las Alas) Indang, United States International University (USIU - Africa), Cavite State University Main Campus (Don Severino de las Alas) Indang CPEN 21A, United States International University (USIU - Africa) APT 2020, CUNY New York City College of Technology EMT 1250, Alightle_ResearchImprovementIdeas_11192018.docx, Vaughn College of Aeronautics and Technology, Stepping Stone Lab Three - Branches Reflection.docx, Rasmussen College, Florida HIM 141 HIM 12, Vaughn College of Aeronautics and Technology FLT 241, Southern New Hampshire University IT 511, Purdue University, Northwest MGMT ORGANIZATI, Southern New Hampshire University QSO 345, 07 01 DEANlNG CORRELATIO NAL AND DIFFERENTIAL RESEARCH METHODS 147 this prove th, 16 In Zimbardos Stanford Prison Experiment young psychologically normal men were, Diet Description Issues Cabbage Soup Diet Lemon Detox Macrobiotic Diet Raw Food, Fall Prevention in Healthcare Settingsxx.docx, AI Neural network basics - Elements of AI.pdf, 8 3315 Trial test 9 Written final exam Module Basic Mathematics General Stenden, 85 The LEAD program was initiated in 2011 with objective of reducing criminal, Question 4 What is Petes first decision as president of the company Selected, PC1 module 7 In vitro assays in preclinical DD.docx, Example of Binomial Distribution Example of Binomial Distribution Martin, Terminale Bac Pro suites numriques squence.doc, Run through the following sorting algorithm and determine the largest number.

4. The power supply for CMOS ICs ranges from 3V to 15V. 0000000933 00000 n Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). This laboratory report was done mainly for the study of the logic gates.

T=N$TR1$!/zS?k1lRD,^v \z/bu11JN8or0Fsm:v"&71lRZHf'8& 5C\! 3) Then reconstruct the circuit above using only NOR gates. Exceeding the specified maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the power demanded from it. 1) Find the Boolean equation for the logic circuit shown in Figure 5-5. A 0 1 0 0 1 1 The common ECL type is designated as the 10,000 series. The following logic families are the most frequently used. In practice, this is advantageous since

a. N _rels/.rels ( j0@QN/c[ILj]aGzsFu]U ^[x 1xpf#I)Y*Di")c$qU~31jH[{=E~ %PDF-1.5 % 0000001745 00000 n i - >$ublIoX&,3jYfDP76iB%l4e/+[. ciJyYH_PVb53](ZmBFAS~B`k:e5[WUx5e,e(L,GC ,]GW= lx(p% Your algorithm will ask the user to provide the. You can construct all of the other basic gates using only NAND or only NOR gates. If you wish to confirm your prediction, repeat step 6 for the NOR gate. WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. 0000008112 00000 n WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. 0 to 0.8V = Logic 0 and lights the L indicator. 7. 0000000016 00000 n Doing this lab will show us how to develop adder design as well as hierarchical design which. 0T\N-U9xgsb&. Now change the control signal to a 50Hz bipolar input (+5V, -5V). WebLab Report: Digital Logic Lab Report: Digital Logic Introduction Gates-----At the most basic level, gates are simply electronically controlled switches. TTL has a well-established popularity among logic families. LAB TASK#1: Implement the following logic circuit on logic trainer.

Use of switches as inputs and light emitting diodes (LEDs) or LCD (liquid crystal WebExperiment 1 - Basic Logic Gates with Logisim Objectives: 1. WebDraw the logic diagram of the network and verify its operation using a truth table. WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit.

xref At any given moment, every terminal is in one of the two binary WebBasic Logic Gates. As those 2) Complete the Truth table (Table 5-1) and measure the voltages of VA, VB, and VX for each input/output. We see some defects as the logic is settling, like tiny spikes, but it eventually settles to the same value as your behavioral simulation. 313 Menu Interface Testing For option selection cursor and option list please, Do not leave children unattended inside the vehicle They could unknowingly ac, 291 Unicode and ASCII code Java uses Unicode a 16 bit encoding scheme, To count the number of cells in column E that contain the text lawn sign in cell, Depreciation expense on the office furniture and fixtures was 7800 for the year, if it is at least 2 standard deviations away from the mean We can therefore, 4 Evaluation of Windows Azure Security The strategy used in this study is based, According to s 760A the main objects of Ch 7 are to promote confident and, Question 20 If a corporation has two classes of shares outstanding rate of, address Address Address But focus on last But focus on last octet octet Last, 2 Describe the Pruitt Prep ferry 3 Who was on the ferry that we have seen in the.

WebA logic gate is an elementary building block of a digital circuit. For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. <]>> One of the most important contributing factors towards loading is the input capacitance of the following gate. 0000005472 00000 n 0000011943 00000 n This interval of time is defined as the propagation delay of the gate. Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. 0000003695 00000 n Sometimes, the term loading is used instead of fan-out. To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. These basic logic gates can be implemented with SSI integrated circuits (ICs) or as part of more complex MSI or VLSI circuits. WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. A Truth Table defines how a combination of gates will react to all possible input combinations.

0000003198 00000 n 297 0 obj<> endobj ;F//lC_*FY =j1/$*]gBm=Lt7'VU6UV>>G_"* t?^,why+_b^OCjp5*.f ] vWMq3^JbMnq:NZ;S